perf(wire): parallelize per-wire vertex emission with rayon
Step 2 of the wire pipeline cold-open optimization plan. Extracts the per-wire vertex expansion into a free function and drives it from `from_batch` via `par_iter().map(...).reduce(...)`. Per-wire emission is already independent (no shared state, no order coupling — `block_cache` groups wires by style upstream), so the parallel-then-concatenate shape is correctness-preserving. Cold-open wire upload now scales with available cores; a drawing with many short wires shows the biggest win. Also collapses two near-identical emission loops (`from_batch`, `build`) into one shared helper. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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Hakan
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522b123d82
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1 changed files with 102 additions and 162 deletions
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@ -25,6 +25,7 @@
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use crate::scene::wire_model::WireModel;
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use crate::scene::wire_model::WireModel;
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use iced::wgpu;
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use iced::wgpu;
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use rayon::prelude::*;
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/// Allocate a VERTEX buffer with `mapped_at_creation` and write `data` directly
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/// Allocate a VERTEX buffer with `mapped_at_creation` and write `data` directly
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/// into the mapped slice. Skips the intermediate staging copy that
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/// into the mapped slice. Skips the intermediate staging copy that
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@ -143,6 +144,91 @@ pub struct WireGpu {
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pub vp_scissor: Option<[f32; 4]>,
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pub vp_scissor: Option<[f32; 4]>,
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}
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}
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/// Expand one `WireModel` into its flat vertex stream (6 verts per finite
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/// segment). Pulled out so both the single-wire and batched paths share the
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/// same emission logic, and so the batched path can `par_iter().flat_map`
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/// across wires on cold open.
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fn emit_wire_vertices(wire: &WireModel, color: [f32; 4]) -> Vec<WireVertex> {
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let pat0 = [
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wire.pattern[0],
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wire.pattern[1],
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wire.pattern[2],
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wire.pattern[3],
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];
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let pat1 = [
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wire.pattern[4],
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wire.pattern[5],
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wire.pattern[6],
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wire.pattern[7],
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];
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let half_width = wire.line_weight_px * 0.5;
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let n = wire.points.len();
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let seg_count = n.saturating_sub(1);
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if seg_count == 0 {
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return Vec::new();
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}
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let mut dists = vec![0.0_f32; n];
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for i in 1..n {
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let p = wire.points[i - 1];
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let q = wire.points[i];
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if !p[0].is_finite() || !q[0].is_finite() {
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// plinegen=false: reset to 0 at the first real point after a NaN separator.
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dists[i] = if !wire.plinegen && !p[0].is_finite() && q[0].is_finite() {
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0.0
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} else {
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dists[i - 1]
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};
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} else {
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let dx = q[0] - p[0];
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let dy = q[1] - p[1];
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let dz = q[2] - p[2];
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dists[i] = dists[i - 1] + (dx * dx + dy * dy + dz * dz).sqrt();
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}
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}
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let mut vertices: Vec<WireVertex> = Vec::with_capacity(seg_count * 6);
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for i in 0..seg_count {
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let a = wire.points[i];
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let b = wire.points[i + 1];
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if !a[0].is_finite()
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|| !a[1].is_finite()
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|| !a[2].is_finite()
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|| !b[0].is_finite()
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|| !b[1].is_finite()
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|| !b[2].is_finite()
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{
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continue;
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}
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let dist_a = dists[i];
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let dist_b = dists[i + 1];
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let make = |which_end: f32, side: f32| -> WireVertex {
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let dist = if which_end < 0.5 { dist_a } else { dist_b };
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WireVertex {
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pos_a: a,
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pos_b: b,
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which_end,
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side,
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color,
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distance: dist,
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half_width,
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pattern_length: wire.pattern_length,
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_pad: 0.0,
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pat0,
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pat1,
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}
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};
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vertices.push(make(0.0, -1.0));
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vertices.push(make(1.0, -1.0));
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vertices.push(make(1.0, 1.0));
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vertices.push(make(0.0, -1.0));
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vertices.push(make(1.0, 1.0));
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vertices.push(make(0.0, 1.0));
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}
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vertices
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}
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impl WireGpu {
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impl WireGpu {
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pub fn new(device: &wgpu::Device, wire: &WireModel) -> Self {
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pub fn new(device: &wgpu::Device, wire: &WireModel) -> Self {
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let mut g = Self::build(device, wire, wire.color);
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let mut g = Self::build(device, wire, wire.color);
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@ -158,85 +244,23 @@ impl WireGpu {
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if total_segs == 0 {
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if total_segs == 0 {
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return vec![];
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return vec![];
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}
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}
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let mut vertices: Vec<WireVertex> = Vec::with_capacity(total_segs * 6);
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for wire in wires {
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// Parallel per-wire vertex emission. `flat_map_iter` keeps memory peak
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let color = wire.color;
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// sane (one Vec<WireVertex> per wire, then concatenated) while letting
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let pat0 = [
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// rayon spread CPU work across cores. Ordering is preserved.
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wire.pattern[0],
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let vertices: Vec<WireVertex> = wires
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wire.pattern[1],
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.par_iter()
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wire.pattern[2],
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.map(|wire| emit_wire_vertices(wire, wire.color))
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wire.pattern[3],
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.reduce(Vec::new, |mut acc, mut chunk| {
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];
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if acc.is_empty() {
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let pat1 = [
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chunk
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wire.pattern[4],
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} else if chunk.is_empty() {
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wire.pattern[5],
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acc
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wire.pattern[6],
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wire.pattern[7],
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];
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let half_width = wire.line_weight_px * 0.5;
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let n = wire.points.len();
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let capped_segs = n.saturating_sub(1);
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// Cumulative arc-length per point.
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let pts_len = capped_segs + 1;
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let mut dists = vec![0.0_f32; pts_len];
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for i in 1..pts_len {
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let p = wire.points[i - 1];
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let q = wire.points[i];
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if !p[0].is_finite() || !q[0].is_finite() {
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// plinegen=false: reset to 0 at the first real point after a NaN separator.
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dists[i] = if !wire.plinegen && !p[0].is_finite() && q[0].is_finite() {
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0.0
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} else {
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dists[i - 1]
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};
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} else {
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} else {
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let dx = q[0] - p[0];
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acc.append(&mut chunk);
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let dy = q[1] - p[1];
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acc
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let dz = q[2] - p[2];
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dists[i] = dists[i - 1] + (dx * dx + dy * dy + dz * dz).sqrt();
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}
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}
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}
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});
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for i in 0..capped_segs {
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let a = wire.points[i];
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let b = wire.points[i + 1];
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if !a[0].is_finite()
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|| !a[1].is_finite()
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|| !a[2].is_finite()
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|| !b[0].is_finite()
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|| !b[1].is_finite()
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|| !b[2].is_finite()
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{
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continue;
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}
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let dist_a = dists[i];
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let dist_b = dists[i + 1];
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let make = |which_end: f32, side: f32| -> WireVertex {
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let dist = if which_end < 0.5 { dist_a } else { dist_b };
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WireVertex {
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pos_a: a,
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pos_b: b,
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which_end,
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side,
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color,
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distance: dist,
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half_width,
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pattern_length: wire.pattern_length,
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_pad: 0.0,
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pat0,
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pat1,
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}
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};
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vertices.push(make(0.0, -1.0));
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vertices.push(make(1.0, -1.0));
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vertices.push(make(1.0, 1.0));
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vertices.push(make(0.0, -1.0));
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vertices.push(make(1.0, 1.0));
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vertices.push(make(0.0, 1.0));
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}
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}
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if vertices.is_empty() {
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if vertices.is_empty() {
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return vec![];
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return vec![];
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@ -261,92 +285,7 @@ impl WireGpu {
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}
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}
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fn build(device: &wgpu::Device, wire: &WireModel, color: [f32; 4]) -> Self {
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fn build(device: &wgpu::Device, wire: &WireModel, color: [f32; 4]) -> Self {
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let pat0 = [
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let vertices = emit_wire_vertices(wire, color);
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wire.pattern[0],
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wire.pattern[1],
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wire.pattern[2],
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wire.pattern[3],
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];
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let pat1 = [
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wire.pattern[4],
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wire.pattern[5],
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wire.pattern[6],
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wire.pattern[7],
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];
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let half_width = wire.line_weight_px * 0.5;
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let n = wire.points.len();
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let seg_count = if n >= 2 { n - 1 } else { 0 };
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let mut vertices: Vec<WireVertex> = Vec::with_capacity(seg_count * 6);
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// Precompute cumulative arc-length at each point.
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// NaN points do not contribute to arc length — they are separator sentinels.
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let mut dists = vec![0.0_f32; n];
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for i in 1..n {
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let p = wire.points[i - 1];
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let q = wire.points[i];
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if !p[0].is_finite() || !q[0].is_finite() {
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// plinegen=false: reset to 0 at the first real point after a NaN separator.
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dists[i] = if !wire.plinegen && !p[0].is_finite() && q[0].is_finite() {
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0.0
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} else {
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dists[i - 1]
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};
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} else {
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let dx = q[0] - p[0];
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let dy = q[1] - p[1];
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let dz = q[2] - p[2];
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dists[i] = dists[i - 1] + (dx * dx + dy * dy + dz * dz).sqrt();
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}
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}
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for i in 0..seg_count {
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let a = wire.points[i];
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let b = wire.points[i + 1];
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// Skip segments where either endpoint is non-finite (NaN sentinels
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// from disconnected glyph strokes, or ±inf from Ray/XLine far-point
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// overflow when the direction vector is very large).
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if !a[0].is_finite()
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|| !a[1].is_finite()
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|| !a[2].is_finite()
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|| !b[0].is_finite()
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|| !b[1].is_finite()
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|| !b[2].is_finite()
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{
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continue;
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}
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let dist_a = dists[i];
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let dist_b = dists[i + 1];
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let make = |which_end: f32, side: f32| -> WireVertex {
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let dist = if which_end < 0.5 { dist_a } else { dist_b };
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WireVertex {
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pos_a: a,
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pos_b: b,
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which_end,
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side,
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color,
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distance: dist,
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half_width,
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pattern_length: wire.pattern_length,
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_pad: 0.0,
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pat0,
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pat1,
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}
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};
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// Triangle 1: A(-1), B(-1), B(+1)
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vertices.push(make(0.0, -1.0));
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vertices.push(make(1.0, -1.0));
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vertices.push(make(1.0, 1.0));
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// Triangle 2: A(-1), B(+1), A(+1)
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vertices.push(make(0.0, -1.0));
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vertices.push(make(1.0, 1.0));
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vertices.push(make(0.0, 1.0));
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}
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let label = format!("wire.vbuf.{}", wire.name);
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let label = format!("wire.vbuf.{}", wire.name);
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let vertex_buffer = vertex_buffer_mapped(device, &label, &vertices);
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let vertex_buffer = vertex_buffer_mapped(device, &label, &vertices);
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@ -357,3 +296,4 @@ impl WireGpu {
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}
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}
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}
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}
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}
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}
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